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V386
8-BIT LVDS RECEIVER FOR VIDEO
General Description
The V386 is an ideal LVDS receiver that converts 4-pair LVDS data streams into parallel 28 bits of CMOS/TTL data with bandwidth up to 2.38 Gbps throughput or 297.5 Mbytes per second. This chip is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces through very low-swing LVDS signals. ICS manufactures a large variety of video application devices. Consult ICS for all of your video application requirements.
Features
* Pin and function compatible with the National
DS90CF386, THine THC63LVDF84, TI SN65LVDS94
* Converts 4-pair LVDS data streams into parallel 28
bits of CMOS/TTL data
Pin Assignments
RxOUT22 RxOUT23 RxOUT24 GND RxOUT25 RxOUT26 RxOUT27 LVDS_GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS_VCC LVDS_GND RxIN2RxIN2+ RxCLKINRxCLKIN+ RxIN3RxIN3+ LVDS_GND PLL_GND PLL_VCC PLL_GND PWRDWN RxCLKOUT RxOUT0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VCC RxOUT21 RxOUT20 RxOUT19 GND RxOUT18 RxOUT17 RxOUT16 VCC RxOUT15 RxOUT14 RxOUT13 GND RxOUT12 RxOUT11 RxOUT10 VCC RxOUT9 RxOUT8 RxOUT7 GND RxOUT6 RxOUT5 RxOUT4 RxOUT3 VCC RxOUT2 RxOUT1
* * * * * * * * * *
Fully spread spectrum compatible Wide clock frequency range from 20 MHz to 85 MHz Supports VGA, SVGA, XGA, and SXGA LVDS voltage swing of 350 mV for low EMI On-chip PLL requires no external components Low-power CMOS design Falling edge clock triggered outputs Power-down control function Compatible with TIA/EIA-644 LVDS standards Packaged in a 56-pin TSSOP (Pb free available)
Block Diagram
RxIN0+ RxIN0RxIN1+ RxIN1RxIN2+ RxIN2RxIN3+ RxIN3RxCLKIN+ RxCLKINPWRDWN
PLL LVDS to TTL De-serializer
8 8 8
RED GREEN BLUE HSYNC VSYNC DATA ENABLE CONTROL RxCLKOUT
RxOUT0..27
V386
56-pin TSSOP V386
V386 Datasheet
1
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Pin Descriptions
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Pin name
RxOUT22 RxOUT23 RxOUT24 GND RxOUT25 RxOUT26 RxOUT27 LVDS_GND RxIN0RxIN0+ RxIN1RxIN1+ LVDS_VCC LVDS_GND RxIN2RxIN2+ RxCLKINRxCLKIN+ RxIN3RxIN3+ LVDS_GND PLL_GND PLL_VCC PLL_GND PWRDWN
Type
OUT OUT OUT Ground OUT OUT OUT Ground LVDS IN LVDS IN LVDS IN LVDS IN Power Ground LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN LVDS IN Ground Ground Power Ground IN
Description
Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital ground Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Analog ground LVDS input (-) LVDS input (+) LVDS input (-) LVDS input (+) Analog power Analog ground LVDS input (-) LVDS input (+) LVDS input (-) LVDS input (+) LVDS input (-) LVDS input (+) Analog ground PLL ground PLL power PLL ground Power-down control input. H: Nomal L: Power down, all ouputs are pulled low. Clock output Data outputs on pins (RxOUT0..27) Digital ground Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital power Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27)
26 27 28 29 30 31 32 33
RxCLKOUT RxOUT0 GND RxOUT1 RxOUT2 VCC RxOUT3 RxOUT4
OUT OUT Ground OUT OUT Power OUT OUT
V386 Datasheet
2
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Pin
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Pin name
RxOUT5 RxOUT6 GND RxOUT7 RxOUT8 RxOUT9 VCC RxOUT10 RxOUT11 RxOUT12 GND RxOUT13 RxOUT14 RxOUT15 VCC RxOUT16 RxOUT17 RxOUT18 GND RxOUT19 RxOUT20 RxOUT21 VCC
Type
OUT OUT Ground OUT OUT OUT Power OUT OUT OUT Ground OUT OUT OUT Power OUT OUT OUT Ground OUT OUT OUT Power
Description
Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital ground Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital power Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital ground Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital power Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital ground Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Data outputs on pins (RxOUT0..27) Digital power
.
V386 Datasheet
3
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V386. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item
Supply Voltage, VCC CMOS/TTL Output Voltage LVDS Receiver Input Voltage Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (10 seconds max.) Maximum Package Power Package Derating -0.3 V to +4 V -0.3 V to (VCC+0.3 V) -0.3 V to (VCC+0.3 V) 0 to +70C -65 to +150C 150C 260C 1.61 W (V386) 12.4 mW/C above +25C 15 mW/C above +25C
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (Ta) 3.3 V Supply Voltage (VCC) Receiver Input Range (VIN) Supply Noise Voltage (VN)
Min.
0 3 0
Typ.
25 3.3
Max.
70 3.6 2.4 100
Units
C
V V mVpp
Electrical Characteristics
VDD=3.3 V 10%, Ambient temperature 0 to 70C Parameter
CMOS/TTL DC Specifications
Symbol
VIH VIL VOH VOL VCL IIN
Conditions
Min.
2.0 GND
Typ.
Max.
VCC 0.8
Units
V V V V V
A
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Clamp Voltage Input Current
IOH = -0.4 mA IOL = 2 mA ICL = -18mA VCC
2.7
3.3 0.06 -0.79
VCC 0.3 -1.5 15
V386 Datasheet
4
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Parameter
Output Short Circuit Current
LVDS Receiver DC Specifications
Symbol
0V IOS VTH VTL IIN
Conditions
VOUT = 0V VCM = +1.2 V
Min.
Typ.
Max.
10 -60 +100
Units
mA mV mV
A A
Differential Input High Threshold Differential Input Low Threshold Input Current
Receiver Supply Current
-100 VIN = +2.4 V, VCC = 3.6 V VIN = 0V, VCC = 3.6 V 10 15 220 240 125 140 140 400
Receiver Supply Current (worst case)
ICCRW
CL = 8 pF, f = 65 MHz, worst case pattern CL = 8 pF, f = 85 MHz, worst case pattern
mA mA mA mA
A
Receiver Supply Current (16 Grayscale)
ICCRG
CL= 8 pF, f = 65 MHz, 16 Grayscale pattern CL= 8 pF, f = 85 MHz, 16 Grayscale pattern
Receiver Supply Current (Power Down)
Receiver Switching Characteristics
ICCRZ
Power_Down = Low, Receiver outputs stay low during Power-down mode 20% to 80% VCC, CL= 8 pF 80% to 20% VCC, CL= 8 pF 11.76 f = 85 MHz f = 85 MHz f = 85 MHz f = 85 MHz 25C / 3.3 V 4.5 4 2.0 3.5 8
CMOS/TTL Low-to-High Transition Time CMOS/TTL High-to-Low Transition Time CLKOUT period CLKOUT High Time CLKOUT Low Time Data Setup to CLKOUT Data Hold to CLKOUT RCK+/- to CLKOUT Delay Receiver PLL Setup Time Receiver Power Down Delay Receiver Input Strobe Position for Bit0 Receiver Input Strobe Position for Bit1 Receiver Input Strobe Position for Bit2 Receiver Input Strobe Position for Bit3 Receiver Input Strobe Position for Bit4
CLHT CHLT RCOP RCOH RCOL RSRC RHRC RCCD RPLLS RPDD RSPos0 RSPos1 RSPos2 RSPos3 RSPos4
2 1.8 T 5 5
3.5 3.5 50 7 6.5
ns ns ns ns ns ns ns
14
20 10 1
ns ms
s
f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns
0.49 2.17 3.85 5.53 7.21
0.84 2.52 4.2 5.88 7.56
1.19 2.87 4.55 6.23 7.91
ns ns ns ns ns
V386 Datasheet
5
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Parameter
Receiver Input Strobe Position for Bit5 Receiver Input Strobe Position for Bit6 RxIn Skew Margin (see note and Figure 8)
Symbol
RSPos5 RSPos6 Rskm
Conditions
f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns f = 85 MHz, T = 11.76 ns f = 65 MHz, T = 15.38 ns
Min.
8.89 10.57 300 500
Typ.
9.24 10.92
Max.
9.59 11.27
Units
ns ns ps ps
Note: The skew margins mean the maximum timing tolerance between the clock and data channel when the receiver still works well. This margin takes into acount the receiver input setup and hold time, and internal clock jitter (i.e., internal data sampling window - RSPos). Thyis margin allows for LVDS transmitter pulse position, interconnect skew, inter-symbol interference and intrinsic channel mismatch which will cause the skew between clock (RC+ and RCK-) and data (RX[n]+ and RX[n]- ; n =0, 1, 2, 3) channels.
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
84 76 67 50
Max.
Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
JC
V386 Datasheet
6
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Timing Diagrams
CLKIN/CLKOUT ODD Data In/Data Out EVEN Data In/Data Out T
Figure 1a. "Worst Case" Test Pattern
CLKOUT D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4-7, 12-15, 20-23 D24-27
Figure 1b. 16-Grayscale Test-Pattern Waveforms
CMOS/TTL Output 80% 8pF CLHT 20%
80% 20% CHLT
V386 CMO/TTL Output Load and Transition Times
Figure 2. V386 CMOS/TTL Output Load and Transition Time
V386 Datasheet
7
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
RCOP 2.0 V 0.8 V RCOH RSRC RHRC D0 - D27 Out
2.0 V SETUP 2.0 V HOLD
2.0 V CLKOUT 0.8 V
2.0 V
RCOL
Figure 3. V386 SETUP/HOLD and High/Low Times
RCK
Vdiff=0V RCCD
CLKOUT
1.5V
Figure 4. V386 Clock In to Clock Out Delay
2.0 V
PWRDWN
3.0 V
3.6 V
VCC RCK
RPLLS
CLKOUT
Figure 5. V386 Phase Lock Loop Set Time
1.5 V
PWRDWN RCK IN RPDD Low
Figure 6. V386 Power Down Delay
V386 Datasheet
8
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
TCLK
Clock
Previous Cycle Next Cycle
Data
Rspos0 Min Rspos0 Max Rspos1 Min Rspos1 Max Rspos2 Min Rspos2 Max Rspos3 Min Rspos3 Max Rspos4 Min Rspos4 Max Rspos5 Min Rspos5 Max Rspos6 Min Rspos6 Max
Figure 7. V386 LVDS Input Strobe Position
RCK+/RCKSkew Margin RX[n]+/RX[n]N = 0, 1, 2, 3
Figure 8. Receiver Input Skew Margin
V386 Datasheet
9
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m
V386
8-BIT LVDS RECEIVER FOR VIDEO
Package Outline and Package Dimensions (56-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95
56
Millimeters Symbol
E1 E
A A1 A2 b C D E E1 e L a aaa
Inches* Min Max
Min
Max
INDEX AREA
12 D
-- 1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 8 0 -- 0.10
-- 0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 BASIC 0.018 0.030 0 8 -- 0.004
A 2 A 1
A
* For reference only. Controlling dimensions in mm.
c
-CSEATING PLANE
e
b
aaa C
L
Ordering Information
Part / Order Number V386G V386GT V386GLF V386GLFT Marking V386G V386G V386GLF V386GLF Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel
Package
56-pin TSSOP 56-pin TSSOP 56-pin TSSOP 56-pin TSSOP
Temperature
0 to +70C 0 to +70C 0 to +70C 0 to +70C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
V386 Datasheet
10
5/25/05
Revision 2.0
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e Str e e t , S a n J o s e , C A 9 51 2 6 * t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 * ww w.i c s t . c o m

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